CY28551LFXC-3T【PDF 10/28 页】IC CLOCK INTEL/AMD SIS VIA 56QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1992

6页 7页 8页 9页 [10页]11页 12页 13页 14页

CY28551-3

....................Document #: 001-05677 Rev. *D Page 18 of 28

by the clock generator to correctly sample the PCI_STP#

assertion, this time is 10 ns minimum.

PCI_STP# De-Assertion

The de-assertion of the PCI_STP# signal is to function as

follows. The de-assertion of the PCI_STP# signal is to be

sampled on the rising edge of the PCIF free running clock

domain. After detecting PCI_STP# de-assertion, all PCI,

stoppable PCIF and Stoppable PCIEX clocks will resume in a

glitch free manner. The PCI and PCIEX clock resume latency

should exactly match the 1 PCI clock latency required for

PCI_STP# entry. The stoppable PCIEX clocks must be driven

high within 15ns of PCI_STP# de-assertion. The drawing

below shows the appropriate relationship. The Tsu_cpu_stp#

is the setup time required by the clock generator to correctly

sample the PCI_STP# de-assertion, this time is 10 ns

minimum.

CLKREQ# Clarification

The CLKREQ# signals are active low input used for clean

stopping and starting selected SRC outputs. The outputs

controlled by CLKREQ# are determined by the settings in

de-bounced signal in that its state must remain unchanged

during two consecutive rising edges of DIFC to be recognized

as a valid assertion or de-assertion. (The assertion and

de-assertion of this signal is absolutely asynchronous)

CLKREQ# Assertion

All differential outputs that were stopped are to resume normal

operation in a glitch free manner. The maximum latency from

the de-assertion to active outputs is between 2-6 PCIEX clock

periods (2 clocks are shown) with all CLKREQ# outputs

resuming simultaneously. If the CLKREQ# drive mode is

tristate, the all stopped PCIEX outputs must be driven high

within 10 ns of CLKREQ# de-assertion to a voltage greater

than 200mV

CLKREQ# De-Assertion

The impact of asserting the CLKREQ# pins is all DIF outputs

that are set in the control registers to stoppable via assertion

of CLKREQ# are to be stopped after their next transition.

When the control register CLKREQ# drive mode bit is

programmed to '0', the final state of all stopped PCIEX signals

is PCIEXT clock = High and PCIEXC = Low. There is to be no

change to the output drive current values, SRCT will be driven

high with a current value equal 6 x Iref, When the control

final state of all stopped DIF signals is low, both PCIEXT clock

and PCIEXC clock outputs will not be driven

Tsu _pc i_ stp# >

10ns

PC I_ STP #

PC I_ F

PC I

P C IE X 10 0M H z

Figure 7. PCI_STP# Assertion

PCI_STP#

PCI_F

PCI

PCIEX 100MHz

Tdrive_PCIEX <15 ns

Figure 8. PCI_STP# De-Assertion

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式